1. Field of the Invention
The present invention relates to the fabrication and design of semiconductor devices generally, and particularly to the use of thin film transistors (TFTs) in complementary circuits with improved electrical characteristics.
2. Brief Description of The Prior Art
A thin film transistor (TFT) "stacked" or fabricated on top of another type of transistor is a device configuration which promotes high density of various types of circuitry. Because of the relatively small size of thin film transistors, it is economically advantageous to use them in integrated circuitry where device density is of paramount importance. These types of circuits include gate arrays and memory chips such as Static Random Access Memory (SRAM). A typical design of an SRAM makes use of both p-type and n-type field effect transistors (FETs) with their drain terminals connected to each other. This particular circuit, commonly known as complementary configuration, uses TFTs as driving transistors stacked on top of another transistor which are then used to construct SRAM devices. TFTs used as driving transistors in SRAMs must have the requisite current drive capabilities that would ensure stable and reliable operation.
A major problem arises with the use of TFTs in complementary devices. As schematically illustrated in FIG. 1, in a complementary configuration where the drain regions of p-type and n-type transistors are connected in series, a p-n junction or diode is created between the two transistors. This "diode effect" can be readily understood by reviewing FIGS. 1-2A in conjunction with the text below.
As illustrated in FIG. 1, a complementary circuit 1 generally comprises a p-channel transistor 2 connected in series with an n-channel transistor 3. Between the drains 4, 5 of the complementary transistors, a p-n junction 6 is formed creating a `diode effect`. This diode effect presents an energy threshold barrier that allows only currents having sufficient energy to flow through the p-n junction. Consequently, a larger voltage is needed for the complementary device to operate properly.
In order to better understand the cause of the diode effect in complementary devices using TFTs, it is helpful to briefly review the physical construction of such a device. Illustrated in FIG. 2 is a drawing of the complementary device of FIG. 1. As shown in FIG. 2, the complementary device has an n-type polysilicon layer 16 that is used to define the boundaries of the gate region 19. FIG. 2 also shows the source region 20 of the p-channel transistor. The source region 22 of the n-channel transistor is likewise shown in FIG. 2.
Also shown in FIG. 2 and 2A, a second n-type polysilicon layer 23 also located between transistor 17 and transistor 18 would come into contact with drain regions 24 and 25 of transistors 17 and 18 respectively. This layer serves to interconnect the drain regions of transistors 17 and 18. N-type polysilicon interconnecting layer 23 and drain region 24 of p-channel transistor 17 form a p-n junction 26 that can be clearly seen in the prior art complementary device shown in FIGS. 2 and 2A. Also shown in FIG. 2 and 2A is the drain region 25 of the n-channel device which comes in contact with n-type polysilicon layer 23.
The diode effect becomes extremely problematic in many electronic circuits such as SRAM circuits where a p-channel TFT is used to drive an n-channel FET such that the drain regions of each device are adjacent to each other thus forming a p-n junction with each other or with a polysilicon layer. For example, in a common circuit configuration, an NMOS FET driven by a PMOS TFT FET is used as a pull-down transistor whose drain is electrically and physically in contact with the drain of the PMOS TFT. When these complementary devices are used in SRAM memory cells, the `diode effect` severely diminishes memory cell stability and soft error immunity.
FIG. 3 shows a schematic of an SRAM cell consisting of two complementary devices and access transistors 7 and 8. The p-n junction effect is represented by diodes 9 and 10. This particular circuit schematic depicts the pull-down transistors 11 and 12 as n-channel devices, e.g. NMOS transistors. The pull down transistors are being driven by TFT PMOS transistors 13 and 14 whose source terminals 15A and 15B are commonly wired to power source V.sub.cc. The I.sub.D currents shown flowing through each complementary device must be large enough to overcome the threshold energy barrier created by the p-n junction diodes. This additional current demand caused by the existence of the p-n junction serves to reduce the high density of transistors normally associated with semiconductor devices that are designed with TFTs. Not only will the number of SRAM cell in a memory integrated circuit be reduced, but each cell will dissipate more power as a result of the diode effect. Therefore, the integrated circuit memory chip becomes less energy efficient as a result of the diode effect.
One suggestion to solve the diode effect when using TFTs in a stacked configuration with other transistors is based on manipulating the geometry of the TFT's channel region. However, this technique only reduces somewhat the diode effect by making the p-n junction "leaky." It does not completely or substantially eliminate the diode effect. Further, this technique requires various modifications in the TFT's fabrication process increasing the manufacturing cost of the complementary device.
Thus, what is needed and would be useful is a complementary device which uses TFTs in a stacked configuration fabricated in such a manner as to completely or substantially eliminate the diode effect while exploiting the high speed and high density characteristics of TFTs with little or no increase in fabrication cost.